Memory segmentation is a method of organizing computer memory that divides the memory into variable sized segments. Typically, each memory segment stores information containing common attributes such as location, size, type (i.e. stack, code or data) and protection characteristics.
In an Intel.RTM. architecture microprocessor, memory is organized into one or more variable length segments. Each memory segment comprising up to four gigabytes in size. Segmentation allows management of the logical address space by providing data and code relocatability and efficient sharing of global resources. The segmentation unit provides four levels of protection for isolating and protecting application programs and the operating systems from conflict in the address space. The Intel.RTM. architecture microprocessor hardware enforced protection allows the design of systems with a high degree of integrity.
Memory segments in an Intel.RTM. architecture microprocessor are addressed using linear addresses. A linear address consists of an effective address combined with a segment base address. The segment base address is stored in a segment register. The effective address is formed by summing all of the addressing components (base, index, displacement) into an effective address with an effective address calculator.
When the effective address calculator of the microprocessor generates an effective address to address a memory segment, the microprocessor must test the effective address to ensure that it falls within the memory segment to be accessed. If the effective address does not fall within the memory segment to be accessed, a segment violation occurs and the processor enters an exception handling routine.